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From the Cycclone III handbook:
Additionally, you have to keep the placement rules for voltage referenced I/O standards. B.T.W., address and command lines are also using a voltage reference SSTL-2 Class I standard with DDR RAM. I didn't see an explicitely statement in the handbook, if VREF is also needed for SSTL output only pins, I would follow the Quartus Pin Planner in this regard.
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I'm very appreciated to your reply!
'address and command lines are also using a voltage reference SSTL-2 Class I standard with DDR RAM' , that is to say all four VREFB pins in one bank should connect to the VCC125? in this case,another question occurs, all pins in bank3 and bank4 is not enough for DDR sdram, that means I should use another banks for connection of the DDR, is that right?
another question,what is B.T.W.?
I'm really a beginner,give me some suggestion. thank you for your help!
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