Honored Contributor
Honored ContributorFrom the Cycclone III handbook:
--- Quote Start --- If you do not use all of the VREF groups in the I/O bank for voltage referenced I/O standards, the VREF pin in the unused voltage referenced groups can be used as regular I/O pins. --- Quote End --- --- Quote Start --- When VREF pins are used as regular I/Os, they have higher pin capacitance than regular user I/O pins. This will have an impact on the timing if the pins are used as inputs and outputs. --- Quote End --- Additionally, you have to keep the placement rules for voltage referenced I/O standards. B.T.W., address and command lines are also using a voltage reference SSTL-2 Class I standard with DDR RAM. I didn't see an explicitely statement in the handbook, if VREF is also needed for SSTL output only pins, I would follow the Quartus Pin Planner in this regard.
