Hold time violations in ALTLVDS_RX with 300 MHz input clock

We have added input delay constraints as suggested in the user guide. The constraints are based around a 300 MHz DDR interface where the data and clock are center aligned.

Note that hold time violations are still present.

Please note that hold time violations are within ALTLVDS_RX IP.

We have also found that the hold time violations disappear if we modify constraints for 333 MHz clock instead of 300 MHz (see altlvds_rx_333.sdc).

Maybe there is a problem with specifying fractional clock periods?