Hold time violations in ALTLVDS_RX with 300 MHz input clock

Hi Kenny

note that in our "real" design the ALTLVDS_RX is actually driving logic. We are seeing the same hold-time violations as are visible in the empty example project. I attached this empty example project to provide an easily reproducible test case. Please let us know which timing constraints we should use if you still think that the constraints "might not be appropriate".

I had a look at the link you provided. Please note that we are seeing hold-time violations. The document you provide seems to discuss the case of setup-time violations, i.e. if the input clock rate is too fast too fast for the design/FPGA. The document does not talk about hold time violations.

Again, the problem is that we are seeing hold-time violations at 300 MHz which do not appear when constraining for 200 MHz or 400 MHz input clock rate. We need your support to understand why these hold-time violations occur and how to fix them.

Thanks