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Hi,
I have a two banks of registers, with bankA driving bankB. Both run from the same 6.4ns clock (from a PLL). I'm getting a hold error because it appears that the delay between the registers is extremely small(no logic in between, only routing). There is some clock skew between the clock arriving at bankA and the clock arriving at bankB. Once you add up the clock skew and hold time requirement for bankB, it's much larger than the data delay. This only happens to a few registers. Each bank is 80 registers.
I do have the 'all paths' turned on. Is there some other way that I can solve this issue. It's a single clock net driving both register banks so I'm not sure what else I can do.
How can I set a minimum delay or is that not a good idea?
Regards
MT
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Hi,
how large is your clock skew ? Is a global line used for the clock ? You can check that in the compilation report section "Fitter" -> "Global and other Fast signals". If the clock is not global defined it as global.
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