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Altera_Forum's avatar
Altera_Forum
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13 years ago

High VCCIO and consumption

Hello,

I am currently working on a Stratix IV GX and I have to push VCCIO higher than 3.3V (I am aware this not a good idea concerning the longterm lifetime) when other VCCs stay at there initial values .

When I start the FPGA with VCCIO at 3.0 V, my external power supply indicates a 0.4A consumption. When I set it up to 3.1V (+0.1V) the indicated consumption is 0.8A (x2). When 3.3V, the consumption is already about 3A, even if I set the next line:

>> set_global_assignment -name stratix_device_io_standard "3.3-v lvcmos"

Why the consumption is so high and grow exponentialy?

Moreover:

When I start the FPGA with a particular VCCIO value, the consumption is lower than when I start it with a lower VCCIO and making it reaching up the same value.

When I start the FPGA with a high VCCIO value, the consumption does not stay at a stable value. For exemple with VCCIO=3.5V, I(t0)=4.5A, a couple hours later I(t0+2h)=5A

Can somebody help me to understand what happend? Is it something to do (in Quartus II maybe) to allow higher VCCIO than 3.3V without such a consumption?

Regards.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    No one on this list will be able to provide any definitive answer. You're essentially "violating your warranty", so "your mileage may vary" :)

    Why do you need to operate the VCCIO at the higher voltage?

    If you have a device external to the FPGA that requires a 3.6V interface, then you can interface to the FPGA using BusSwitches or dual-power rail buffers.

    If you can explain the problem you are trying to solve, perhaps the forum can offer alternative solutions that do not violate the operating conditions of the device.

    Cheers,

    Dave