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Altera_Forum
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11 years ago

High Speed Transceiver CDR Lock Time

I am investigate the possibility that using high speed SERDES of FPGA (such as Stratix IV or V GT) to cope with burst traffice in Passive Optical Network. In the Table 1. of Altera's Whitepaper ...
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Altera_Forum
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10 years ago

Hi HE_HAO,

Generally we should refer to the specs in the SIV device datasheet. As stated in datasheet, if your CDR is in Auto locking mode, then minimum CDR lock time to get valid data is 4000ns. However, if the CDR is in manual locking mode, which is you control the locking, the CDR lock time spec is max 4000ns. I believe the CDR lock time mentioned in the white paper is achieved using manual control of CDR lock mode. Note the in manual mode, the CDR lock time is calculate from rx_locktodata assertion to valid data recovered.