High Speed time/pulse counter application

The Altera LVDS receivers can operate at up to 1Gbps, i.e., they can sample a logic signal at 1ns period (or slightly shorter). I use this scheme to interface to 1GHz clock rate ADCs, and have had no issues.

The Altera gigabit transceivers can be operated at 3.125Gbps on the low-end Altera devices, and at up to 10Gbps on the high-end devices. I'm currently evaluating these interfaces for use at 5Gbps and higher.

Since you only care about time, then it sounds like you could use one of these options.

If you draw a timing diagram of the pulses, and provide specific details about what information you would like, eg., shortest pulse to expect, fastest update rate. The more accuracy you desire, the more expensive the FPGA. How did you want to gather this information; external TI microcontroller, NIOS microcontroller on the FPGA?

If you want to look at data sheets, then the low-end FPGAs with LVDS and transceivers are the Cyclone IV GX, the Arria II GX (and I think there are versions now with V in the names), and the high-end devices are the Stratix IV and V GX (and GT).

Cheers,

Dave