High speed DAC/ADC for Dev Kits?

Intersting similarity to my current work.

We have our own mezzanine card with DAC/ADC running at 560MHz dual channels.

The clocking is same to both ADC channels. The fpga receives the dual channels and processes them in parallel at 280Mhz.

The bottle neck is the fpga speed. anything more than 300Mhz is unrealistic for stratix 4. In your case you might need to process 4 channels in parallel inside fpga. you can break the channels on DDR pins or serdes.

One problem might be when DAC/ADC channels lose order(alignment) if not synchronised.