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Altera_Forum
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16 years ago

High speed Clock generation by ALTPLL Cyclone III

hello, i have a problem to use the high speed clock generated by ALTPLL. I have the Cyclone III EP3C25F324 FPGA starter board. There is an 50MHz on-board oscillator for PLL. I need a high spee...
Altera_Forum's avatar
Altera_Forum
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16 years ago

thank you for your answer.

I simulated the logic function with the timing simulation tools, it's all correct with clock of 800MHz, above this frequency was then false. I don't understand why did the MegWizard Plug-In Manager (configuration of PLL output clock) allow to set to the clock up to 1300MHz, if this clock can not be distributed by Cyclone III? Is it a bug of Altera?