High speed Clock generation by ALTPLL Cyclone III

I'm willing to believe the hardware manual, that a clock frequency above 500 MHz can't be distributed by the Cyclone III clock network. Furthermore, you won't be able to operate logic at 800 or even 1200 MHz because the propagation delays don't allow feedback without timing violations.

Faster FPGA families (e.g. Stratix IV) achieve up to 800 MHz core clock frequency. Direct 1200 MHz logic operation isn't an option even with the fastest FPGA. But multi-bit parallel processing and double data rate I/O interfaces may be able to achieve the intended logic operation speed anyway.