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Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi, How to choose the speed grade in an FPGA or CPLD?

Hi I've a lot of questions about FPGAs and CPLDs speed grade, I want to generate a pulse of 3 ns acording to an event, which means that I need at least a 333 MHz clock, either external or u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I really appreciate the orientacion now I have more ideas, I prefer to keep it simple and don't do unnecessary things, I'm going to document myself and hope that if anything else comes up you can help me as always XD thanks