Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi, How to choose the speed grade in an FPGA or CPLD?

Hi I've a lot of questions about FPGAs and CPLDs speed grade, I want to generate a pulse of 3 ns acording to an event, which means that I need at least a 333 MHz clock, either external or u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Keep in mind that whatever pulse you manage to generate will not be like any existing equipment. The "minimum" effort output pulse is to route the input signal directly back out to an output signal. However, there will be a minimum pulse width requirement. I have no idea what that is, because it would never be a good idea to do that in a 'real' design. If you wanted such a pulse, why not simply use an external comparator, or high-speed logic level translator?

You need to talk to your customers and ask what they really want. There's no point in you delivering something useless, and then having that reflect badly on you. You need to be up-front and tell them its a bad idea, or have them explain what it is they really want.

Cheers,

Dave