Hi, How to choose the speed grade in an FPGA or CPLD?

Thanks for the counting advices, that's just what I need, and you're right the final goal is to count the events

The current system has many stages because they can't just use the original signal to be an input for the counter, I know that I don't have to implement a discriminator in the FPGA, but in the end is my laboratory working for another laboratory, and to have this signal is one thing that they ask us to do, not sure if is only for see it or to be an input for another equipment or for comparison purposes, maybe they think that is necesary and that's why they want it

As far as I know they're interested in the count, there is a posibility of not implement this signal, after more meetings the details will be decided, but for now I have to consider that there is a chance, and I will have to do it, I wanted to be prepare and think in a way, thats why I began to wonder whats realy means speed degree