Hi, How to choose the speed grade in an FPGA or CPLD?

when you said "see" another pulse, you mean the output I want to generate?, and yes, I want to count, but in general what I want to to do is use an FPGA to replace a set of laboratory equipment that does the same thing (discriminator, logic unit), in order to compare, I have to generate the same output that the discriminator does

Thanks for the information, I'm going to read it, and I forgot to tell that the time between events is at least of 50 ns, and I have to study more about synchronous and asynchronous systems, because I believed that if my sampling method used or not a clock defined an synchronous or asynchronous system