Hi, How to choose the speed grade in an FPGA or CPLD?

Thanks for answer XD

This is basically what I need, my input is a TTL signal: an aleatory pulse of 2.5 V amplitud and between 17 ns and 20 ns duration (the rising time is betwen 800 ps and 1 ns), I care for events, when I see one, I have to generate an output with a 3.3 ns duration, the amplitud its not realy important it may be 3.3 V or 2.5 V. I was thinking in sample this input with a 300 MHz clock, (external or generated from pll) because is the duration I need for my output, and its

enough for see the event.

But then I began to wonder about the speed grade, if the FPGA or CPLD can suport the frequency

I don't have experience with LVDS outputs so I will have to read about it before ask something, but It gives me the idea of working asynchronously, maybe this is not correct because I don't completely understand the concept of speed grade, but, if my FPGA is speed grade -5 (delay of 5 ns through macrocell) this means that If I see an event and generated an output signal, this signal have a delay of 5 ns without the need of a 200 MHz clock? I don't know if this make sense or I explain my idea, but thanks for reading it