Hi, How to choose the speed grade in an FPGA or CPLD?

Hi,

speed grade information in documentation is becoming border line useless, because modern devices are just so damn complicated.

Synthesize your design (or a simplified version of it, if you don't have it yet) and see if it can meet the timing constrain.

The simulation and synthesis tools can be downloaded for free from Altera's website, so you can do a lot of evaluation before commiting to a FPGA.

Note 1: using the DDR output cells, you maybe able to generate a 3 ns pulse using a 166 MHz clock.

Note 2: The various speed grades of the same model are pin compatible, so you can leave the speed grade decision until you need to assemble the PCB.

Note 3: It's just a bit more complicated, but a PCB can be designed to allow for different FPGA models (smaller or bigger), within the same FPGA family and package.