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NKuma10's avatar
NKuma10
Icon for New Contributor rankNew Contributor
7 years ago

Hi All, I have some doubt regarding FPGA I/O banks.

I'm working on FPGA with I/O banks configured as 3.3-V LVCMOS with current strength of 2ma. I have a requirement to change the current strength to 16ma for some of the signals in this I/O bank which...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hello Andrew , Thank you giving opportunity to look at issue, Can I assume few things from your input , i) You are not plan to use LVDS in the board using FPGA. Correct ? ii) The VCCIO of bank 5 and 6 connected to the 3.3V. Also Can I assume VREFBx pin is not used for reference voltage ? Correct If my above assumption yes , I don’t think so there is issue to connect the 3.3V bank 5 and bank 6 . In the datasheet can you refer page 7 for the max apply VCCIO ? Note : VCCA must connected to the 2.5V. May I know why you think bank 5 and 6 need to use only for LVDS ? Thank you, Regards, Sree