Hi,
Sorry, I can't read chinese. Understood that you are chinese customer but I still your help to continue to explain in English.
Your scope clk measurement make sense. If transceiver channel is not properly calibrated then the output clock is expected to be bad.
Assuming you didn't change much and connect everything correctly in the example design and the design did work in A10 dev kit board. we can then conclude that
- Quartus Ethernet example design (ok)
- Loopback test run is not a bring up requirement as it's not required on A10 dev kit board
- The failure should be related to either your board design or your overall hardware system bring up issue
From your signal_tap result, looks like the transceiver calibration process keeps on being interrupted and then restart again. This process repeat forever until your performed loopback testing.
- I think I mentioned this before - there are 2 things that may affect transceiver calibration
- clk_usr - this transceiver calibration clock is not stable or free running during FPGA power up period or somehow the clock is interrupted during transceiver calibration process
- Can you review your board setup and cross check to monitor this clock on your scope ?
- A system reset is being performed during transceiver calibration process
- This one you need to review your system reset control. Can you add delay to your system reset to ensure you only release it after transceiver calibration is completed
- Another debug option is modify example design to connect transceiver reset controller IP reset input to Quartus "In and source and Probe" (ISSNP) IP to isolate transceiver reset from your board system reset
Worst come to worst if we still can't find the issue on your board setup then maybe you need to implement additional steps to perform "serial loopback" action once before you can start Ethernet operation on your board
Thanks.
Regards,
dlim
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