Forum Discussion
Occasional ContributorHelpless about 1588V2
Occasional ContributorHi Deshi and team
1. It is the master port phy being calibration , and the process is：
“being calibration(re_cal_busy=1)----> calibration finish (re_cal_busy=0)----->being calibration(re_cal_busy=1)----->calibration finish (re_cal_busy=0)----->............
Repeat the process untill perform PHY_serial_loopback on "slave" , The maste port stop calibration ,and "re_cal_busy=0 " and the other signals is correct。
（ I take an video for "Autorun analysis" in the appendix，plese check out )
2. This test resul never appear in A10 dev kit board;
By the way , can you read in Chinese?
Occasional ContributorHi Deshi and team
I have use external hardware equipment to send some data to the master port ,and Rx channel to ensure "rx_is_lockedtodata" and "rx_ready" signal asserted high for one time before running 1588 test.
Then when I perform "TEST_1588 0 1 10G " , it is fail , and the master port (0 port) phy is being calibarated repeat.
But I don't think it is related to loopback test requirement, My project running on the A10 dev kit board,it is never being calibarated.
- mark_lee
Hi Deshi and team
1 I measurement the signal "phy_rx_recovered_clk " when the phy is being calibrated , the "phy_rx_recovered_clk[0] and phy_rx_recovered_clk[1] ” is too bad , like this pictrue:
2. perform Physerial_loopback (0 port or 1 port ), the ”“phy_rx_recovered_clk[0] and phy_rx_recovered_clk[1] ” is good , like this pictrue:
