Helpless about 1588V2

Hi,

Thanks. These are good debug sharing but I am a bit confused on your signal_tap debug result.

• You mentioned you performed PHY_serial_loopback on port 1 but it somehow affect the transceiver status on port 0 ?
• Or you need to perform PHY_serial_loopback on both port 0 and port 1 before you can get 1588 test run working ?

My suspect is your port 0 or port 1 Rx channel is still stuck in reset, causing 1588 test to fail.

• Performed loopback test asserted CDR lock (rx_is_lockedtodata), then released Rx channel from reset and asserted (rx_ready). Rx channel is now ready to run 1588 test

I am not sure channel stuck in reset is due to

• MAC is operating in bidirectional mode. (unidirectional mode option is turned off in MAC IP)
• Or somehow transceiver PHY reset controller IP is holding Rx channel in reset
• Or this could be due to the example design tcl script functional write up where it expect user to perform internal loopback test before proceed to external test

To isolate whether this is related to "example design tcl script coding style issue" or "loopback issue"

• You can try to use external hardware equipment to send some data to port 0 and 1 Rx channel to ensure "rx_is_lockedtodata" and "rx_ready" signal asserted high for one time before running 1588 test
• If 1588 test passed, then we know somehow this is related to transceiver reset sequence requirement
• If 1588 test still failed, then we know it's related to loopback test requirement. User must performed one time loopback test before running actual Ethernet test

Thanks.

Regards,

dlim