Forum Discussion

mark_lee's avatar
mark_lee
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Helpless about 1588V2

I run the project "LL10G_1G_10G_LINESIDE_1588v2" on the demo board "Arria 10 SOC Development Kit" 1588V2 thranceive an receive are OK ; I made project run on my board(10AS066H3F34I2SG) , it is can...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


  1. We don't support FPGA internal loopback from one transceiver channel to another transceiver channel. That's why you get design compilation error.
  • We only support FPGA internal loopback within the same transceiver channel from Tx channel back to Rx channel


Just would like to follow up with you - did you have a chance to play around with different signal_tap triggering setup to observe different signal_tap result between passing and failing case ?

  • Any latest debug update to share with me ?


Thanks.


Regards,

dlim


  • mark_lee's avatar
    mark_lee
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    1. I had run the 1588 test project on my board with Optical fiber between 0 port and 1 port , when I run Signal Tap to get 0 port phy interface signal , I get an abnormal signal , the phy is being calibrated：

    Under these circumstances，running 1588_TEST , Fail

    2. Every time after running ”TEST_PHYSERIAL_LOOPBACK 1 10G 5000“ , The Signal Tap get an normal signal about 0 port phy interface :

    Under these circumstances，running 1588_TEST , succes