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mark_lee's avatar
mark_lee
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Helpless about 1588V2

I run the project "LL10G_1G_10G_LINESIDE_1588v2" on the demo board "Arria 10 SOC Development Kit" 1588V2 thranceive an receive are OK ; I made project run on my board(10AS066H3F34I2SG) , it is can...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI Mark,


May I know

  • stp_1588_TEST_success.stp = 1588 test passed result ?
  • stp_1588_TEST_fail.stp = 1588 test failed result ?


The reason I asked is due to I am seeing weird result when compared to golden reference signal_tap result from ref design doc (page 14). Attached is the result comparison that you can check it out yourself.


I suspect is either

  • (A) Something is still wrong with your board or system reset control on 1588 ref design "channel_reset_n" and "master_reset_n" ports
  • Or (B) your signal_tap result is capturing the system test run at the wrong time (like before the system is stable or after test run completed)


We now know that signal_tap is working on your board. You can then play with signal_tap trigger feature to try detect following expected signal behaviour

  • For instance, your signal_tap result shown transceiver channel is still stuck in reset and ready signal haven't asserted high
  • both ch0 and ch1 rx_islockedtodata signal doesn't assert high which means Rx channel CDR doesn't detect correct 10G data and lock yet
  • both ch0 and ch1 rx_enh_blk_lock signal doesn't assert high as well which highly due to CDR is still loose lock ?
  • ch0 link_fault status signal also asserted high which is bad


Pls try play around with trigger function and re-capture signal_tap result for both passing and failing cases then we can compared the result again.

  • You can do so yourself to compare with page 14 expected signal_tap result in parallel
  • Then we can exchange debug opinion to discuss further


Thanks.


Regards,

Deshi



mark_lee's avatar
mark_lee
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Deshi

  • stp_1588_TEST_success.stp = 1588 test passed result ? YES
  • stp_1588_TEST_fail.stp = 1588 test failed result ? YES
  • mark_lee's avatar
    mark_lee
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi Deshi and team

    I have try to make 1588V2 channel 0 loopback to channel1 on the chip without Optical module。My code is:

    " assign rx_serial_data[0] = tx_serial_data[1] ;

    assign rx_serial_data[1] = tx_serial_data[0] ；”

    then compilation, I get error about this :

    Error(11654): Output port "VOP" of "HSSI_PMA_TX_BUF" cannot connect to HSSI port "RX_P_BIDIR_IN" of "HSSI_PMA_TX_BUF" for atom "altera_eth_multi_channel_1588_inst|CHANNEL[1].altera_eth_channel_1588_inst|phy|xcvr_10gkr_a10_0|CHANNEL|DATAPATH_10G.NATIVE_PHY_10G_1588_644_LS.native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf".
    Error(11654): Output port "VOP" of "HSSI_PMA_TX_BUF" cannot connect to HSSI port "RXP" of "HSSI_PMA_RX_BUF" for atom "altera_eth_multi_channel_1588_inst|CHANNEL[1].altera_eth_channel_1588_inst|phy|xcvr_10gkr_a10_0|CHANNEL|DATAPATH_10G.NATIVE_PHY_10G_1588_644_LS.native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_buf.inst_twentynm_hssi_pma_rx_buf".
    Error(11654): Output port "VOP" of "HSSI_PMA_TX_BUF" cannot connect to HSSI port "RXP" of "HSSI_PMA_CDR_PLL" for atom "altera_eth_multi_channel_1588_inst|CHANNEL[1].altera_eth_channel_1588_inst|phy|xcvr_10gkr_a10_0|CHANNEL|DATAPATH_10G.NATIVE_PHY_10G_1588_644_LS.native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll".
    Error(11654): Output port "VOP" of "HSSI_PMA_TX_BUF" cannot connect to HSSI port "RXP" of "HSSI_PMA_CDR_PLL" for atom "altera_eth_multi_channel_1588_inst|CHANNEL[0].altera_eth_channel_1588_inst|phy|xcvr_10gkr_a10_0|CHANNEL|DATAPATH_10G.NATIVE_PHY_10G_1588_644_LS.native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|native_10g_1588_644_ls_inst|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll".
    Error(11654)

    HOW can I make channel 0 loopback to channel 1 on the chip?
    thanks a lot !