Hi Mark,
Pls use the original working ref design without design modification. Just change the FPGA OPN and pin location to match your board only.
- Once getting the design to work then only feel free to modify the design
Let's debug your following statement first
- When 1588 test failing I can't trigger and capture anything , as the ip core never running
Can you share with me the signal_tap screenshot/file when the 1588 test is failing ?
- I want to know what's the exact signal condition that you see from signal_tap in test failed condition.
Let me explain. Which scenario that you are facing here ?
- Scenario A :
- Signal_tap is clocked by "xgmii_clk_312_5". Once the xgmii clock presented on your board, signal_tap should start capture something (be it good or bad signal status) if you set the signal_tap trigger condition to capture everything xx. Don't set trigger condition like trigger on rising edge or faling edge
- The only reason signal_tap will stop working is there is no clock on xgmii_clk_312_5. Signal_tap will complain "waiting for clock". Are you seeing scenario A ?
- No clock could be due to your board stop supplying input clock to FPGA or FPGA IOPLL loose lock or your design is stuck in reset. Then you can check further from here
- Scenarion B :
- Signal_tap detected "xgmii_clk_312_5" and start capturing data.
- But you set signal_tap trigger condition on some signal and the signal didn't trigger causing nothing capture on your signal_tap because it's still waiting for signal trigger.
- Pls set the signal_tap trigger condition to capture everything xx. Don't set trigger condition like trigger on rising edge or faling edge
- Then we see what's signal status result on the signal_tap
Thanks.
Regards,
dlim
Occasional Contributor
