Forum Discussion
Occasional ContributorHelpless about 1588V2
Occasional ContributorHi Deshi and team
1. I use the design is build by my workmate , he is reference to the example " Arria 10 Scalable 10G Ethernet MAC+ Native PHY with IEEE1588v2 Design “；
2.My design is running 1588V2 test success on the demo board "Arria 10 SOC Development Kit" ;
3. MY design running "TEST_SMA_LB" and " TEST_PHYSERIAL_LOOPBACK" test success on my board;
4. Every time running ”TEST_PHYSERIAL_LOOPBACK“，and then running "TEST_1588" 。1588TEST is success 。 THis the only method to made 1588TEST success now 。IF didnot running "TEST_PHYSERIAL_LOOPBACK" before "TEST_1588" , 1588 test fail, and the statistic log always show zero value;
5. Clock On my board is :
(1) clock to FPGA clkusr (100Mhz );
(2) ref_clk_10g (644.53MHz);
(3) mm_clk (100MHz);
(4) ref_clk_1g ( "no clock input " ),
There have no clock 125Mhz for the "ref_clk_1g" on my board , In my design did not need 1g test.
THANKS
Regards,
mark
Occasional ContributorHi Deshi and team
In addition :
I set the "IOPLL" out2 is 125Mhz ,and use it as the "IOPLL2 ” ref_clk_input , IOPLL2 output the "tod sync" and "sampling clock".
- mark_lee
Hi Deshi
1. When 1588 test passing I can trigger and capture the signal_tap debug signals；（The "1588_test_passing" file is in the enclosure)
2 .Whe 1588 test failing I can trigger and capture anything , as the ip core never running .
- mark_lee
Hi Deshi and team
I have modify my board clock by program the chip Si5338A, and now my board clock is :
(1) clock to FPGA clkusr (100Mhz );
(2) ref_clk_10g (644.53MHz);
(3) mm_clk (125MHz);
(4) ref_clk_1g ( 125MHz );
but the 1588 test is never improve
- mark_lee
Hi Deshi and team
1. I had run the 1588 test project on my board with Optical fiber between 0 port and 1 port , when I run Signal Tap to get 0 port phy interface signal , I get an abnormal signal , the phy is being calibrated：
Under these circumstances，running 1588_TEST , Fail
2. Every time after running ”TEST_PHYSERIAL_LOOPBACK 1 10G 5000“ , The Signal Tap get an normal signal about 0 port phy interface :
Under these circumstances，running 1588_TEST , succes
