Forum Discussion
Occasional ContributorHelpless about 1588V2
Regular ContributorHi Mark,
I presume you are still using below ref design "unchanged" or you had modified the design ?
Let's clarify your problem statement before we discuss about debug plan :
- Your latest update mentioned 1588 hardware testing sometime pass, sometime failed, right ?
- Does the failure occurs randomly or always after 2nd time of 1588 hardware testing ?
- Does reset the system and retest 1588 makes it to pass again ?
- When 1588 test failed, does the statistic log always show zero value ? This looks to me your design or system is stuck rather than receive wrong/bad data issue
For the debug plan, similar approach applied as I explained to you earlier on the other post
- Does your board provide clean and stable clocking to ref design mm_clk (125MHz), ref_clk_10g (644.53MHz), ref_clk_1g (125MHz) ?
- Does your board supply (100Mhz - 125MHz) clock to FPGA clkusr pin that's in charge to provide clocking to transceiver channel power up calibration ?
- The ref design comes with stp1.stp debug signal_tap file. Can you trigger and capture the signal_tap debug signals for both passing and failing condition and share with me the signal_tap files ? We can then review the signal_tap files to see which status signal is failing and debug further from there
Thanks.
Regards,
dlim
Occasional ContributorHi Deshi and team
1. I use the design is build by my workmate , he is reference to the example " Arria 10 Scalable 10G Ethernet MAC+ Native PHY with IEEE1588v2 Design “；
2.My design is running 1588V2 test success on the demo board "Arria 10 SOC Development Kit" ;
3. MY design running "TEST_SMA_LB" and " TEST_PHYSERIAL_LOOPBACK" test success on my board;
4. Every time running ”TEST_PHYSERIAL_LOOPBACK“，and then running "TEST_1588" 。1588TEST is success 。 THis the only method to made 1588TEST success now 。IF didnot running "TEST_PHYSERIAL_LOOPBACK" before "TEST_1588" , 1588 test fail, and the statistic log always show zero value;
5. Clock On my board is :
(1) clock to FPGA clkusr (100Mhz );
(2) ref_clk_10g (644.53MHz);
(3) mm_clk (100MHz);
(4) ref_clk_1g ( "no clock input " ),
There have no clock 125Mhz for the "ref_clk_1g" on my board , In my design did not need 1g test.
THANKS
Regards,
mark
- mark_lee
Hi Deshi and team
In addition :
I set the "IOPLL" out2 is 125Mhz ,and use it as the "IOPLL2 ” ref_clk_input , IOPLL2 output the "tod sync" and "sampling clock".- mark_lee
Hi Deshi
1. When 1588 test passing I can trigger and capture the signal_tap debug signals；（The "1588_test_passing" file is in the enclosure)
2 .Whe 1588 test failing I can trigger and capture anything , as the ip core never running .
- mark_lee
Hi Deshi and team
I have modify my board clock by program the chip Si5338A, and now my board clock is :
(1) clock to FPGA clkusr (100Mhz );
(2) ref_clk_10g (644.53MHz);
(3) mm_clk (125MHz);
(4) ref_clk_1g ( 125MHz );
but the 1588 test is never improve
