Help:How to assign the ports?

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I have set the constraints in the TimeQuest Timing Analyzer, after full compiling ,the TimeQuest Timing Analyzer summary shows some unconstrained paths, such as "Unconstrained Input Port Paths","Unconstrained Output Ports "and "Unconstrained Output Port Paths". You know that the constraints in the TimeQuest Timing Analyzer have clock sets, input and output delay sets, min and max delay sets, and so on. I have just constrained the clock,do i need to set other constraints and what do the constraints mean i need to set?

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It is recommended to use set_input_delay and set_output_delay -max and -min for all device pins (ports). You can instead use set_max_delay and set_min_delay, but those are not the preferred constraints for I/O. Chapters 6 and 7 cover this.

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In my work, i use some DFF and the clock of the dff is other asynchronous signals provided by logic cells , and i get the warnings say that the clock of the dff is not constrained when i set constraints, so i created clock and set the targets to the clock of dff ports ,then the warning disappeared, is it wright that i constraint them as clock? I don't think it is wright ,but the warning gone, why?

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"...the clock of the dff is other asynchronous signals provided by logic cells..." sounds like you are using a ripple or gated clock. That is usually a bad idea. What you said about the warning going away makes me think it is a ripple clock.

If you are driving a register's clock input with anything other than a direct connection to a device pin or PLL, see my posts at http://www.alteraforum.com/forum/showthread.php?t=754. The thread is particularly about divided-down clocks, but the information applies to any ripple or gated clock. Some of the information there is about the Classic Timing Analyzer, but all the design guidelines and cautions apply to either analyzer. The main difference with TimeQuest is different reporting of an unconstrained ripple clock (a clock driven by a register) and no message about gated clocks (clocks driven by combinational logic).