Help:How to assign the ports?

Thanks very much, Brand.

I have read the Quartus handbook, Volume 3, Section II carefully today. Now i know the TimeQuest Timing Analyzer much better than before. There are still something i don't understand.

I have set the constraints in the TimeQuest Timing Analyzer, after full compiling ,the TimeQuest Timing Analyzer summary shows some unconstrained paths, such as "Unconstrained Input Port Paths","Unconstrained Output Ports "and "Unconstrained Output Port Paths". You know that the constraints in the TimeQuest Timing Analyzer have clock sets, input and output delay sets, min and max delay sets, and so on. I have just constrained the clock,do i need to set other constraints and what do the constraints mean i need to set?

In my work, i use some DFF and the clock of the dff is other asynchronous signals provided by logic cells , and i get the warnings say that the clock of the dff is not constrained when i set constraints, so i created clock and set the targets to the clock of dff ports ,then the warning disappeared, is it wright that i constraint them as clock? I don't think it is wright ,but the warning gone, why?

I change the file.sdc to another one which has different constraints, actually,more constraints, the waveform is wrong. In a project ,what's the standard of the constraints?

Hope you can help me .

Thanks very much.

Regards.