Help:How to assign the ports?

You need to start by reading the relevant documentation.

Read through chapters 6, 7, and 8 in the Quartus handbook, Volume 3, Section II. Those chapters cover the Classic Timing Analyzer, TimeQuest Timing Analyzer, and a comparison between the analyzers. You don't have to understand everything in those chapters. Look through them to get a basic familiarity with what is available, and read carefully the parts that look most likely to be relevant to your present needs.

There are on-line demos, training, and design examples. For the Classic Timing Analyzer, start at http://www.altera.com/support/software/quartus2/timing/sof-qts-timing.html. For TimeQuest, start at http://www.altera.com/support/software/quartus2/timequest/tq-spt-index.html.

For each particular assignment in the Assignment Editor, look for an on-line help page for that assignment. You can usually find the help page by typing the assignment name exactly in the Help Search tab.

To be proper for any design, even a MAX II design, you should constrain all paths including I/O. However, there are many assignments in the Assignment Editor that you don't need on every design.

TimeQuest does not use any information from the Assignment Editor. It gets its constraints from an SDC file.

Don't be overwhelmed by the amount of information. Start by focusing on what you obviously need to know now.