Help with problem

If you know the functions (derived from truth table) for bcd to excess3 and bcd to graycode, model the HDL designs using any of the 3 modelling techniques (gate level, dataflow, behavioral). Also model a 2:1 mux.

let the modules be 2_1mux.v , bcd2excess3.v and bcd2gray.v

The following is my rough sketch of how the final design will be

// module and port declaration

//instantiations

excess3.v (.input(bcd),.en(!s0),.ouput(excess3))

gray.v (.input(bcd),.en(s0),.ouput(gray))

2_1mux.v (.data1(excess3),.data2(gray),.sel(s0),.output(output))

HTH..