Help with modelsim

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Am I correct in saying that VGA_CLK is never assigned a value?

Check your errors and warnings. There you may find something that may help you find the problem.

--- Quote End ---

Should I assign the value on the testbench? I can post the whole testbench and than maybe you can see were I went wrong.

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LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY test_vga_vhd_tst IS

END test_vga_vhd_tst;

ARCHITECTURE test_vga_arch OF test_vga_vhd_tst IS

-- constants

-- signals

SIGNAL CLOCK_50 : STD_LOGIC := '0';

SIGNAL KEY : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL RESET_N : STD_LOGIC;

SIGNAL VGA_B : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL VGA_BLANK_N : STD_LOGIC;

SIGNAL VGA_CLK : STD_LOGIC;

SIGNAL VGA_G : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL VGA_HS : STD_LOGIC;

SIGNAL VGA_R : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL VGA_SYNC_N : STD_LOGIC;

SIGNAL VGA_VS : STD_LOGIC;

COMPONENT test_vga

PORT (

CLOCK_50 : IN STD_LOGIC;

KEY : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

RESET_N : IN STD_LOGIC;

VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

VGA_BLANK_N : OUT STD_LOGIC;

VGA_CLK : OUT STD_LOGIC;

VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

VGA_HS : OUT STD_LOGIC;

VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

VGA_SYNC_N : OUT STD_LOGIC;

VGA_VS : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

i1 : test_vga

PORT MAP (

-- list connections between master ports and signals

CLOCK_50 => CLOCK_50,

KEY => KEY,

RESET_N => RESET_N,

VGA_B => VGA_B,

VGA_BLANK_N => VGA_BLANK_N,

VGA_CLK => VGA_CLK,

VGA_G => VGA_G,

VGA_HS => VGA_HS,

VGA_R => VGA_R,

VGA_SYNC_N => VGA_SYNC_N,

VGA_VS => VGA_VS

);

CLOCK_50 <= not CLOCK_50 after 20 ns;

RESET_N <= '0', '1' after 50 ns;

init : PROCESS

-- variable declarations

BEGIN

-- code that executes only once

KEY <= "111";

wait for 50 ns;

KEY <= "110";

wait for 50 ns;

KEY <= "111";

wait for 50 ns;

KEY <= "101";

wait for 50 ns;

KEY <= "111";

wait for 50 ns;

KEY <= "011";

wait for 50 ns;

WAIT;

END PROCESS init;

always : PROCESS

-- optional sensitivity list

-- ( )

-- variable declarations

BEGIN

-- code executes for every event on sensitivity list

WAIT;

END PROCESS always;

END test_vga_arch;