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Honored Contributor
Honored ContributorHelp with metastability problem
Hi, I'm working on a vision processing based project at uni using a custom board built around a cyclone III and I am having to modify some vhdl code written by previous years students. A met...
Altera_ForumHonored Contributor
Honored ContributorSo I should run the simulation with my clock speed at frequency of the FPGA and that should let me know if its will run at those speeds? or will I have to do some other timing analysis as well?
# Edit# I tried the simulation, the current clock of the system is 36.15 MHz because the clock is synchronized with the clock from the camera and that is the clock for the camera. So my previous simulations were operating at clock speeds much faster however I adjusted my clock speed used in simulation to be (1/36150000) / 2 ~= 14 ns between every edge (rising and falling) and everything works as expected in simulation. Is this enough for timing anyalysis or do I need to do more? Thanks, Mat.
