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Altera_Forum
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17 years ago

Help with FPGA correlator

Hi everyone, I'm new to FPGA design, and just find out this is the best place for seeking help as well as gaining experience.

I'm designing an FPGA cross-correlator which correlates 8 bits data signal from an ADC with a 66 points reference signal which is hardcoded into the correlator.

My current idea is to use a series of 66 x 8 bits registers, a series of 66 x 8 bits x 8 bits multipliers and an array adder, apparently, this is a time-domain correlator.

file:///C:/Documents%20and%20Settings/tnguyen/My%20Documents/My%20Pictures/correlator%20layout.JPG

I tested a simple version of this correlator (45 points x 5 bits), turned out that the it works well, however, due to the great number of the shift register and multipliers deployed, the full version (66 points x 8 bits) does not fit in the device which I have to stick with.

I'm wondering if anyone could provide me any better idea to reduce the number of gates used, a more concise, neat design, something similar like convolution etc ????

Heard about frequency domain correlator, but not sure if it could help and how to perform the FFT to the digital signal.

tschaggelar (http://www.alteraforum.com/forum/member.php?u=945)has suggested an implementation of a FPGA correlator. Did he really mean only one shift register and one Multiply and Accumulator circuit ??? :confused:

http://www.alteraforum.com/forum/showthread.php?t=1042&highlight=correlation

Thank you very much guys, much appreciate any helps.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The crosscorrelation is like a FIR filtering operation.

    I suggest to use the "Transpose Structure" in order to obtain the lowest critical path delay circuit for the time domain correlator.

    A FFT correlator requieres two's power signal length. This isn't your case.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What are your timing constraints? What sampling frequency do you need? What is the final use of the correlator? Have you considered a clipped correlator (sign bits only)?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks all who has replied my thread. Much appreciate.

    To OrchestraDirector: yeah, I've read the altmult_accum document, understand how it works, but still have no idea how many multiplier-accumulator is required in my design, did you mean 1 ? (1 mult_accum ---> 1 multiplier, right?), then I don't know how could I replace my 66 multipliers by just 1 mult_accum circuit, because most of the time, more than one multiplication needs to be carried out at one moment... Anyway, your suggestion gave me a brand new idea about correlator design. Thank you very much.

    To parrado: yes, I stop thinking about the FFT. However, I don't understand "Transpose Structure", googled it but so few found related result. Could you please provide me some links or documents ? That would be excellent.

    The FPGA correlator is used in a sound velocity sensor device, it correlates a 66 points reference signal (which can be transfered from the ROM of a microprocessor) with signals coming in from an ADC (I'm not sure about the A-D sampling fre, the layout said the A-D clock is 40Mhz, so I assumed the sampling frequency is 40Mhz)

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    http://cnx.org/content/m11918/latest/

    If your correlator operates enough slow to support a sequential solution, as suggested by orchestra director, you must design a FSM that controls the mac (multiply accumulate) for all correlator 66 taps.

    The question is? How much long colud be your sampling period, in order to achieve a good correlator response?

    In case that you need a parallel solution, Look for the Transpose-form FIR filter structure.