help with code for pulse delay?

I recommend doing this in a state machine. A psuedo-code example is shown below, using VHDL 2008 and a record type for the counter signals of enable and done. Of course, you would have to code up the counter as another module, I've just shown the instantiation of the counter. Note the use of the record type making the signals associated with the counter a bit easier to follow. Best, James

--- Quote Start ---

type stateType is (S0, S1, S2);

signal state : stateType;

type counterType is record

done : std_logic;

enable: std_logic;

reset : std_logic;

end record;

signal counter : counterType;

signal pulse : std_logic;

signal dlyReg : std_logic_vector(2 downto 0);

process(all)

begin

if RST then

state <= IDLE;

elsif rising_edge(CLK) then

case state is

when S0 =>

if Trigger then

state <= S1;

counter.enable <= '1';

else

state <= S0;

counter.enable <= '0';

end if;

pulse <= '0';

when S1 =>

if counter.done then

state <= S2;

else

state <= S1;

end if;

counter.enable <= '1';

pulse <= '0';

when S2 =>

pulse <= '1';

counter.enable <= '0';

state <= S0;

end case;

end if;

end process;

process(all)

begin

if RST then

dlyReg <= (others => '0');

elsif rising_edge(CLK) then

dlyReg(0) <= pulse;

dlyReg(1) <= dlyReg(0);

dlyReg(2) <= dlyReg(1);

end if;

end process;

pulseOut <= dlyReg(0) OR dlyReg(1) OR dlyReg(2);

/* ----------------------------------------

Delay counter instantiation

------------------------------------------*/

U3: entity work.DNCNT_INTEGER(BEH)

generic map (

size => PARAM_COUNTS+1

)

port map (

CLK => MCLK,

HRST => counter.reset,

ENABLE => counter.enable,

CNT_VALUE => PARAM_COUNTS,

FLAG => counter.done

);

--- Quote End ---