Honored Contributor
Honored ContributorHello WitFed,
--- Quote Start --- See ug_soc_eds.pdf from Altera site all from top to bottom ! In "HPS Preloader User Guide" is described a process of generation. Binary file will be filled to QSPI to address 0 (4 times of 64K), your program -- to 6x64K), for make binary image use arm-altera-eabi-objdump.exe with address 02000000 that will be used in Preloader to load program to SDRAM. --- Quote End --- I am almost through the whole user guide and the device handbook ;) The point is that I had not the time to do so much research, I would have prefered a easy to follow user guide. Back to the address of the SDRAM... I expected that the address of the SDRAM is on 0x10_0000. I got an advice from an Altera customer support not to mix the quatus II toolchain version. As we are currently develping with the Quartus II V13.1 SP1, I had to make the QSYS design in this version. On the other hand the DS-5, which comes with the Quartus II 14.0 is much more confortable. So have generated the handoff + preloader with V13.1 SP1 and used the "embedded command shell" from V14.0 --> bad idea. He also told me to use the 14.0 toolchain as the preloader is improved (Pll check and QSPI reset [some problem that bootROM just support 3-byte address mode, but after the first intialization the QSPI flash is configured to 4-byte address mode, so bootROM cannot access it after a reset --> REV.D of the board has a addition logic to do an hardware cold and warm reset, but if a software cold reset occurs, for instance from the FPGA, then QSPI is in the wrong state]added ) He also told me that there must be a bug on the SoC DIE, because if the CSEL pin are not configured to 0x00, one internal PLL might hung up... they fixed already, but the Development Kit are delivered with the old chips. So I followed his advices and changed to V14.0, rebuild the design and downloaded the preloader on the QSPI, et voi lá: I got some prints on the UART port, but with and ECC error, but it is a first success :D in this long winded process!!! U-Boot SPL 2013.01.01 (Sep 24 2014 - 13:17:14) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 800 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 50000 KHz CLOCK: QSPI clock 200000 KHz SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB SDRAM: ECC Enabled SF: Read data capture delay calibrated to 1 (0 - 3) SF: Detected N25Q512 with page size 65536, total: 67108864 Info: SDRAM ECC SBE @ 0x00021534 Error: SDRAM ECC DBE occurred sbecount = 4 erraddr = 00021534 dropcount = 00000000 dropaddr = 00000000 # ## ERROR# ## Please RESET the board# ## Maybe I should change the address of the SDRAM to 0x200_0000. Has anyone another suggestion? Kind regards, Roland
