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Altera_Forum's avatar
Altera_Forum
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15 years ago

help! problem with a program

begin

state <=# 1 stop;

shift_start <=# 1 1'b1;

index <=# 1 index + 2'b01;

case (index)

2'b00: sig_num <=# 1 4'b1011;

2'b01: sig_num <=# 1 4'b1101;

2'b10: sig_num <=# 1 4'b1110;

2'b11: sig_num <=# 1 4'b0111;

endcase

end

this segment program above have a doubt with me.when it runs ,if the index=00, the sig_num is 4'b0111; but i think it should be 4'b1011.

can someone tells me why?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Now, index == 2'b11, the value in port 'd' of sig_num reg(or d-flip-flop) is 4'd0111

    Then an active edge of clock comes,

    index turns to 2'b00,

    SIMULTANEOUSLY, sig_num turns to 4'b0111(for 'd' to 'q').

    HDL describes hardware structure, all statements in a block, especially non-blocking assignments in synchronious block are taking effects simultaneously.