Help needed on verilog delay on quartus

Hi,

I'm working on a Uni project and I'm trying write a bit of code on Quartus II using verilog that will, when a 1bit register (init) is changed from "0 to 1" OR "1 to 0", set 1bit output (HS) to 1 for three clock cycles then set it back to 0.

The init reg is set by a FSM and HS reg initialises a handshake FSM.

I've been trying for a couple of days now but I just can't seem to figure it. :(

Was planing on using the wait statement but quartus says:

Warning (10193): Verilog HDL unsupported feature warning at delay.v(9): Wait Statement is not supported and is ignored :confused:

If anyone can help me it would be greatly appreciated.