Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

help me to translate verilog to vhdl

hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

but I have a syntax error when I'm compiling some verilog source (few lines) in a .vhd file !

The smart way, is to translate my few verilog lines to vhdl code..

--- Quote End ---

Hi,

you can't use verilog syntax in a VHDL-file. You need separate files for your VHDL and Verilog stuff.

Kin regards

GPK

Recent Discussions