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Honored Contributor
Honored Contributorhelp me to translate verilog to vhdl
hello, is there anyone expert in both verilog and vhdl?? i did learn only vhdl..help me to translate these codes into vhdl.. `timescale 1ns / 1ps module mctrl( input clk, ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- but I have a syntax error when I'm compiling some verilog source (few lines) in a .vhd file ! The smart way, is to translate my few verilog lines to vhdl code.. --- Quote End --- Hi, you can't use verilog syntax in a VHDL-file. You need separate files for your VHDL and Verilog stuff. Kin regards GPK
