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Altera_Forum
Honored Contributor
15 years agoI understand, i used pll with inclk0 = 50MHz and 2 output clock that 500, 400MHz. Can u tell me why i can not create the second output clock 400MHz??? it said that :
"Cannot implement the request PLL". "Cause : Request mult/div factor not achievable". And the output clock parameter : mul = 20 , div = 3 why???(50*20/3 != 400MHz) if right , they must be mul = 8, div = 1 because 50MHz * 8 = 400.