Help: HSMC and I2C

With weak pull-up, SDA and SCL rise time may be too slow. You can slow down the I2C master timing in this case or use external strong pull-ups. They should me connected to 3.3V VCC to achieve a higher level without level translation. SCL could also use a push-pull driver, if no clock stretching is implemented by the slave. (Most likely it is neither used by the slave nor supported by the master).