help for driving ccd imgae sensor with 5v output

Thanks for reply.

i want to design ccd image acquisition system.In my

design ,i took Kodak KAI-1020 sensor and altera

cycloneii FPGA. cycloneii fpga produces ccd drive

signals. But problems is the driving timing signal

level is +5 v and the cyclone II io output singal level is 3.3v.

i want to insert a buffer(74ac04) between the FPGA and the CCD.

In the kai-1020 handbook,it use 74a04 as a buffer .But the reference design it use lattice isp1032e(cpld) chip.

Based on the following considerations,i took the 74ac04 as the buffer between the FPGA and the KAI-1020 sensor. is it wrong?

Thanks

Sheng Li

detail information about ccd drive singal level and 74ac04 key information

1.Pulse Amplitudes -ccd drive signal 

Clock Min. Amplitude (volts) Coupling Min. Coupling Capacitor Value (µF) Max. Coupling Capacitor Value (µF)

SH 3.5 DC -- --

H1 4.7 AC 0.1 0.47

H2 4.7 AC 0.1 0.47

SA 4.7 AC 0.01 0.47

SB 4.7 AC 0.01 0.47

R 4.7 AC 0.01 0.47

T 4.7 AC 0.01 0.47

V1 4.0 AC 0.01 0.47

V2A 4.0 AC 0.01 0.47

V2B 4.0 AC 0.01 0.47

FD 4.0 AC 0.1 0.47

2. 74ac04-buffer

Vcc +5v

High Level Input Voltage 2.75v

Low Level Input Voltage 1.65v

High Level Output voltage 4.86v

Low Level Output voltage 0.36v