CShek1New Contributor7 years agohello sir can u help me, i am displaying 3 digits using seven segment display, everything is done i got output(used verilog HDL code) but the problem is during power up it is reset to "000". previous values are not stored. so what is the solution
3 RepliesReplies sorted by Most LikedTrickyOccasional Contributor7 years agoFPGAs are volatile, so state is always lost on resetCShek1New Contributor7 years agok thank you for reply, but what is the solution sir.,TrickyOccasional Contributor7 years agoWhat are you trying to do? Why do you need to retain state after power down?
TrickyOccasional Contributor7 years agoWhat are you trying to do? Why do you need to retain state after power down?
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