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CPain1's avatar
CPain1
Icon for New Contributor rankNew Contributor
5 years ago

Hello! Any help with a counter issue on my .VWF file.

I am creating a 4-bit up/down counter with the JK FF 74112. When I created my .VWF my counter is not counting properly. Any advice on what could be the problem? I have attached some pics of my program. (My clock needed to be 25MHz, I am using the DE2-115 board, so I pinned my clock to the ENETCLK_25) I am very new at this!! Thank you

2 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    It's working correctly, but you've got your endianness backwards in the simulation. QA is your LSB but your "Count" output has it as the MSB.

    #iwork4intel

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi Charlene,

    Seem like there no problem with the simulation, the logic works properly as it is bidirectional counter. Can see there down and up counting. Input low the count output is counting down from most significant bits. Same goes to high input starting from MSB