Forum Discussion
Deshi_Intel
Regular Contributor
6 years agoHi,
If you refer to HBM2 user guide doc page 21 - core clock frequency explanation :
- The maximum supported core frequency depends on the device speed grade and timing closure of the core interface clock within the FPGA.
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20031.pdf
I am not sure where do you see the 370MHz spec but that most likely is theoretically max supported spec but it still depends on user design timing closure to determine the achievable Fmax.
Thanks.
Regards,
dlim