Having a clock issue

Question

Im rather new to quartus and having trouble with one of my assignments.

I am designing a moore counter using 8 states and 3 jkff2 flip flops. Im almost certain that everything is wired up correctly but my simulation only shows the first state and almost seems that the circuit is not running the positive edge clock input.

Im not sure if i have to do anything to set up the clock or if simply creating an input with a controlled waveform is right but for some reason the clock won't shift into the second state.

Any suggestions or help would be greatly appreciated.

Thank you.

altera_forum · Answer

Have you got a testbench? why not post the code and the specific problems, maybe showing a waveform that shows the problem. Otherwise, we can only guess.

altera_forum · Answer

Hi Eddywick  Please post your sample piece of code about your state transitions so that we can find out why the state is stuck at first state itself

altera_forum · Answer

I haven't had to code the assignment yet just using Block Diagram/Schematic File. Attached is the circuit

altera_forum · Answer

The picture is too low resolution to reall read it properly. Please re-attach at a higher res.

altera_forum · Answer

This might be better

Forum Discussion

Having a clock issue

5 Replies

Recent Discussions

Agilex 7 R-Tile RBES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

Agilex 7 R-Tile RES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

Estimate the power consumption of the MAX 10 device 10M08SLV81I7G

Device migration about DD and DA

USB blaster isuee