Hamming window

In terms of Verilog, what you need to implement is a Nth order FIR filter.

The filter's coefficients will be the Hamming window's coefficient.

I am trying to design front end of speech recognition system on FPGA.

I appreciate if you could provide me with useful resources which help me design a hamming window.

Altera provides some filter IP. altera.com/support/examples/verilog/ver-fir-coefficient.html

If you don't have access to the IP then you can build a FIR filter from scratch or get some examples online. Then generate the Hamming Window coefficients. (matlab will do this for you).

Altera has some examples: altera.com/support/examples/exm-list.jsp?cat=dsp_filters_transforms&GSA_pos=4&WT.oss_r=1&WT.oss=FIR%20filter%20example

rbugalho & winfrees,

you suggestions were very useful.

Thank you very much.:)