Hi,
Below is of the follow up question:
- One is for a triple-speed Ethernet MAC/PHY and requires a CML clock; I don’t have a convenient way to create a CML driver; can I drive this ‘CML’ input with an LVDS driver?
Answer:
No, If you configure the IO standard as CML in FPGA, this is NOT recommend to drive this input with an LVDS driver.
If I understand it correctly, your oscillator output connected to FPGA Ethernet PHY reference clock is of LVDS IO standard. If yes, then you may change the IO standard assignment for the FPGA Ethernet PHY reference clock from CML to LVDS using assignment editor. The FPGA Ethernet PHY reference clock supports LVDS IO standard as well.
Regards -SK Lim
Regards -SK Lim
Occasional Contributor
