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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

GXB Reference clocks on Arria 10

I have a design which includes a PCIe endpoint, a 10GE MAC/PHY and a triple-speed ethernet MAC/PHY. Tool-generated pin constraints force the reference clock I/O types to be HCSL for the PCIe, LVDS f...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

​The FPGA is flexible for you to choose which IO standard to use, each standard has its own advantages and disadvantages and it run at a range of difference input/output voltage level.

The supported IO standards of reference clock for Arria 10 are CML, Differential LVPECL, LVDS and HCSL. And yes, you can use either one for difference application. For example, the 10GE, TSE IP and XCVR PHY can use the same IO standard for reference clock in your design.

Regards -SK