Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorGXB Reference clocks on Arria 10
I have a design which includes a PCIe endpoint, a 10GE MAC/PHY and a triple-speed ethernet MAC/PHY. Tool-generated pin constraints force the reference clock I/O types to be HCSL for the PCIe, LVDS f...
SeadogOccasional Contributor
Occasional ContributorYes, I understand that the PCIe reference clock input requires a DC-coupled HCSL driver (I actually wrote that in my original post), and I know that CML and LVPECL use AC coupling (I wrote that as well). And I don't see how those facts support the conclusion that [I] "need to follow the protocol specification".
And it does not address my questions:
- Why are the reference clock I/O constraints different even though the I/O cells are all the same?
- Can I drive all of the AC-coupled reference clock with the same driver type (any driver that meets the stated specifications for the reference clock inputs), and if not, why?
