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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

GXB Reference clocks on Arria 10

I have a design which includes a PCIe endpoint, a 10GE MAC/PHY and a triple-speed ethernet MAC/PHY. Tool-generated pin constraints force the reference clock I/O types to be HCSL for the PCIe, LVDS f...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi, As for the PCIe specification, this is recommended to use the DC coupled with HCSL IO standard. The CML and LVPECL are used on AC coupled link, therefore, you need to follow the protocol specification. Regards -SK